Bridge IP
TrueSilicon’s Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency, power, and area.
Compliant with AMBA 5/4/3 CHI, AXI, AHB, APB & TileLink
Key Benefits
- Available in native verilog (RTL)
- Linting, Synthesis, CDC, RDC are cleaned up.
- 100% Code coverage
- Verified with an expert team using comprehensive and Regression Test Suites
- IP generation tool and programmable model
- Dynamic power saving
- 24X5 customer support
Features
CHI to AXI
- Configurable data widths of all channels.
- Both cacheable and non-cacheable are possible
- Enhanced transaction types for performance optimization
AXI to CHI
- QoS for prioritization of transactions
- Regeneration of ID as per the transactions
- Support ordering requirement of Request Order & Endpoint Order
AXI to AHB
- Support back-to-back transfers.
- Support error detection mechanisms such as timeout interrupt handling.
AXI to APB
- Support different phase shifted frequencies for Master and Slave
- Port data width can be different.
AXI to TileLink
- Configurable data width
- Burst breaking and merging possible
- Support back-to-back transfers
- Handles TileLink A & D channels for request & response respectively
TileLink to AXI
- Support for error codes based on TileLink response types
- Configurable data width
- Response Segregation of read and write
- Supports all valid transfer
TileLink to AXI
- Support all type of transfers
- Early response also possible for write transfer
Deliverables
- Bridge IP
- Master - CHI, AXI, TileLink & AHB
- Slave - CHI, AXI, TileLink, AHB & APB
- IP generator & config tool
- Verilog Test Environment with Verilog Testcases
- IP analysis reports
- Linting report
- Synthesis report
- IP-XACT RDL generated address map
- Simulation script
- IP Block Guide
- Quick Start Guide
